" sequential computers are approaching a fundamental physical
limit on their potential power. Such a limit is the speed of light "
i860XR @ 40 MHz or i860XP @ 50 MHz
Industry standard format (size 6 / 8 TRAM)
16 or 32 MByte memory options
T805 communications processor
Compatible with TRAM motherboards
The TTM110 is a size 6 TRAM module and has a shared memory architecture with 16 Mbytes of 64-bit wide fast DRAM coupled to both an Intel i860XR vector processor, and a T805 transputer to handle I/O and board-to-board communications via four 20Mbit/second serial links. The transputer has 4 Mbytes of private local memory. The two processors exchange data in shared memory, with interrupts and full bus locking for synchronization. The i860XR's memory controller supports sustained data transfer rates in excess of 100Mbytes/sec for pipelined read or write cycles. Peak performance of the TTM110 is 80MFLOPs.
TTM220 is a size 8 TRAM and also has a shared memory architecture with 16 or 32 MByte of 128-bit wide fast DRAM coupled to both an Intel i860XP vector processor, and an SGS-Thomson T805 transputer. The T805 handles I/O and board-to-board communications via four 20Mbit/second serial links. The transputer also has 4 or 8 Mbytes of private local memory. The two processors exchange data in shared memory, with interrupts and full bus locking to synchronize such transactions. The i860XP's memory controller fully supports burst transfers and data rates of up to 393Mbytes/ second continuously for pipelined read or write cycles.
The TTM220 incorporates three innovative features (read caching, snoop filtering and write posting) that maximize shared memory bandwidth. Bus snooping can be disabled for applications where the fixed overhead of cache flushing prior to or following data exchange in shared memory is preferable to the variable overhead of snooping. The TTM220 utilizes the i860XP's MESI (Modify Exclusive Shared Invalid) ensuring cache and memory coherency between the shared memory and the i860XP's cache.
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