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Sundance SMT245 High-speed ST20450 TRAM

• ST20450 Transputer at 40 MHz
• 16KByte internal single cycle 32-bit SRAM
• 4 or 16MByte DRAM
• Two cycle DRAM access (page made)
• 128KByte FLASH EPROM
• Communication via 4 Inmos serial links.
• Sub-system port for transputer networks
• Industry standard Size 2 TRAM
• IEEE 1149.1 JTAG Test Port
• 96-way expansion hardware connector
• Full access to Event, Interrupt and Bus Request (DMA) signals

• High-performance embedded controller
• Distributed process control node for applications including robots and servos
• Multiprocessor system and algorithm development
• Integer intensive applications such as database management
• Seamless and cost-effective upgrade to existing T805 and T425 TRAM based systems
• Direct access to memory for I/O hardware prototyping and development
• Development system when coupled with TRAM motherboard and ST20450 software tools

The SMT245 is a size 2 TRAM containing a 32-bit T450 Transputer running at 40 MHz. This transputer provides up to an order of magnitude performance improvement over T425 based designs, and yet remains compatible with the standard TRAM format. The ST20450 features 16KBytes of single cycle internal SRAM. In addition to this, the SMT245 TRAM may be ordered with 4 or 16MBytes of DRAM making it suitable for both low cost embedded applications, and memory hungry image processing applications. Using page mode DRAM permits memory access in two cycles, giving a peak memory bandwidth of 80MBytes/s.

The SMT245 TRAM also contains a 128KByte FLASH EPROM. In embedded applications, this could be used to store bootstrap and program code, allowing the TRAM to boot itself, and any network it is connected to. The EPROM could also be used to store Xilinx FPGA configuration data, which could be accessed using DMA via the expansion connectors.

All the transputers interface signals are brought to two 48-way expansion connectors, which allow custom interfaces, and prototype development to be carried out using this TRAM. This provides a cost effective way to develop new hardware interfaces using a proven ST20450 core processor and memory design.

• Customer bug list for the ST20450A

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